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NEW QUESTION: 1
Which of the following describes a computer processing architecture in which a language compiler or pre-processor breaks program instructions down into basic operations that can be performed by the processor at the same time?
A. Reduced-Instruction-Set-Computer (RISC)
B. Super Scalar Processor Architecture (SCPA)
C. Complex-Instruction-Set-Computer (CISC)
D. Very-Long Instruction-Word Processor (VLIW)
Answer: D
Explanation:
Very long instruction word (VLIW) describes a computer processing architecture in which a language compiler or pre-processor breaks program instruction down into basic operations that can be performed by the processor in parallel (that is, at the same time). These operations are put into a very long instruction word which the processor can then take apart without further analysis, handing each operation to an appropriate functional unit.
The following answer are incorrect: The term "CISC" (complex instruction set computer or computing) refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way. Later, it was discovered that, by reducing the full set to only the most frequently used instructions, the computer would get more work done in a shorter amount of time for most applications. Intel's Pentium microprocessors are CISC microprocessors.
The PowerPC microprocessor, used in IBM's RISC System/6000 workstation and Macintosh computers, is a RISC microprocessor. RISC takes each of the longer, more complex instructions from a CISC design and reduces it to multiple instructions that are shorter and faster to process. RISC technology has been a staple of mobile devices for decades, but it is now finally poised to take on a serious role in data center servers and server virtualization. The latest RISC processors support virtualization and will change the way computing resources scale to meet workload demands.
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate. A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU core but an execution resource within a single CPU such as an arithmetic logic unit, a bit shifter, or a multiplier.
Reference(s) Used for this question: http://whatis.techtarget.com/definition/0,,sid9_gci214395,00.html and http://searchcio-midmarket.techtarget.com/definition/CISC
and http://en.wikipedia.org/wiki/Superscalar

NEW QUESTION: 2
What is a major differentiator with the IBM Solution for Hadoop - Power Systems Edition, compared to Hadoop on x86?
A. The IBM solution uses MapReduce for scalability to thousands of servers.
B. IBM hardware and software components are customizable for best price/performance
C. The IBM solution provides fixed configurations for hardware and software for easy deployment.
D. The IBM solution uses SSDs and faster interconnects.
Answer: B
Explanation:
Advanced technology for performance and robustness. The hardware and software components in this infrastructure are customizable to allow the best performance or the best price/performance ratio.
Reference:
http://www-03.ibm.com/systems/power/solutions/bigdata-analytics/hadoop/

NEW QUESTION: 3
Refer to the exhibit. The router has been configured with these commands:

What are the two results of this configuration? (Choose two.)

A. The addressing scheme allows users on the Internet to access the WWW server.
B. Hosts on the LAN that is connected to FastEthernet 0/1 will not be able to access the Internet without address translation.
C. The address of the subnet segment with the WWW server will support seven more servers.
D. Hosts on the LAN that is connected to FastEthernet 0/1 are using public IP addressing.
E. The default route should have a next hop address of 64.100.0.3.
Answer: A,B

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